
2008 Microchip Technology Inc.
DS39626E-page 3
PIC18F2525/2620/4525/4620
Pin Diagrams (Cont.’d)
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4525
37
RA3
/A
N
3
/V
RE
F
+
R
A
2/
A
N
2/V
RE
F
-/C
V
RE
F
RA1
/A
N
1
RA0
/A
N
0
MC
L
R
/V
PP
/R
E
3
RB3
/AN9
/CCP2
(1
)
RB7
/KBI
3
/PG
D
RB6
/KBI
2
/PG
C
RB
5
/K
B
I1
/P
GM
RB
4
/KBI
0
/A
N
1
NC
RC6
/T
X/CK
RC5
/SDO
RC4
/SDI/SDA
RD3
/PSP3
RD2
/PSP2
RD1
/PSP1
RD0
/PSP0
RC3
/SCK/SCL
RC2
/CCP1
/P1
A
RC1
/T
1
O
SI
/CCP2
(1
)
R
C
0
/T
1
OS
O/T
13CK
I
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
44-Pin QFN(2)
PIC18F4620
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4525
37
R
A
3/A
N
3/
V
RE
F
+
R
A
2/A
N
2/V
RE
F
-/C
V
RE
F
RA1
/AN1
RA0
/AN0
MC
L
R
/V
PP
/RE
3
NC
RB
7
/K
B
I3
/P
GD
RB
6
/K
B
I2
/P
GC
RB5
/KBI
1
/PG
M
RB4
/K
B
I0
/AN1
1
NC
RC6
/T
X/C
K
RC5
/SDO
RC4
/SDI/SDA
RD3
/PSP
3
RD2
/PSP
2
RD1
/PSP
1
RD0
/PSP
0
RC3
/SCK/SCL
RC2
/CCP1
/P1
A
RC1/T
1OS
I/C
C
P
2
(1
)
NC
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
44-Pin TQFP
PIC18F4620
Note 1:
RB3 is the alternate pin for CCP2 multiplexing.
2:
For the QFN package, it is recommended that the bottom pad be connected to VSS.